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MA: FPGA Design for a Configurable Network Interface Controller

Real-Time Operating Systems (RTOSs) intend to serve applications with well-defined time constraints on embedded systems. Using priority-based scheduling algorithms, they can provide a high predictability concerning the time a task needs to perform its actions. Here, high predictability also has a higher priority than high throughput. Tasks are activated by I/O interrupts through real-time control systems like user interface, sensor or timer interrupts. With the advent of the internet of things (IoT), embedded devices have received more tasks that exhibit significant communication overhead. Interrupts generated by incoming network traffic lead to a preemption of tasks in the RTOS independent of the currently running task’s priority, which leads to increased jitter in systems under high load.

In our research we are looking for approaches to minimize the effect of incoming network traffic on the real time system. This might happen in between the operating system and networking device. To evaluate approaches, a suitable simulation tool has to be developed.

The task for this thesis will be the implementation of a NIC for experimentation purposes in vhdl and its integration into the operating system.

Interested students can develop a personal topic with regards to the specifics of this area.

Some experience with FPGA design in VHDL, operating systems and programming for microcontrollers (in C) is required. Additionally, a high degree of autonomy and some experience with scientific writing is expected.

If this sounds interesting to you, please send me an email with a little bit of background information on yourself, so we can quickly identify a fitting thesis topic together.

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Ilja Behnke
+49 30 314-73884
Room TEL 1203